The invention relates to a program-controlled data processor, more particularly a stored-program data processor for telecommunication systems used for transmitting for binary-coded messages.
In these systems central processing units communicate with central storage units, which receive all data and programs needed for the solution of switching functions. In order to increase the operational reliability of the systems, at least two identically constructed processing units and/or at least two identically constructed storage units are connected in parallel, such that they perform identical functions concurrently and synchronously. The units of information supplied by parallel-running system units are compared, and in case of malfunction the transfer of the units of information to the corresponding system units is prevented.
A program-controlled data processor of known construction, more particularly one employed as a data switching system (see, for example, commonly assigned U.S. Pat. application Ser. No. 61,692, filed Aug. 6, 1970, and now U.S. Pat. No. 3,669,362) is made up of a plurality of system units (FIG. 1 herein). The processing units and at least one storage unit are associated with these system units. The processing units are not connected together, and they communicate with the storage units independently of one another. A storage unit is made up of the working storage (e.g. a core storage containing the data and programs required for the solution of the switching functions), the memory operation control for processing the various storage operations, the storage request control for allocating the storage cycles to the requesting processing units, and the program request control for requesting programs through the processing units. The processing units are connected with the storage units via system standard terminals. The cycle requests of the processing units to the storage units are operated upon in accordance with the priority of their standard terminals connected to the storage. The cycle allocation and the control in the storage for processing storage requests are described, for example, in the commonly assigned U.S. application Ser. No. 57,926, filed July 24, 1970 and now U.S. Pat. No. 3,711,835.
To increase the operational reliability and availability of such a system, it is old to provide all or only specific units at least in duplicate using modular construction. Due to the interchangeability of identical system units, this construction affords the possibility, in case of malfunction of one system unit, of causing the functions thereof to be performed by any one of the other system units. The malfunctioning of at least one of the parallel running system units or an interference with the synchronism is determined by comparing the units of information supplied by the parallel units. If the synchronism of the parallel running system units is interfered with or if the units of information supplied thereto are dissimilar, the result of the comparison will cause the production of a fault signal. The above-referenced U.S. Pat. No. 3,669,362 discloses an arrangement for shunting a plurality of system units employing a comparator shared by a group of system units.
The system units are connected to the comparator continuously, or at least whenever parallel operation is desired. This common comparator is operated through grading or progressive interconnection with respect to time. In other words, parallel-connected system units use the comparator during a storage cycle allocated thereto and in the next storage cycle another group of parallel-connected system units is connected with the comparator. However, such common comparators which, for example, have to serve several pairs of parallel system units simultaneously, can not be employed in processing units operating at very high operating speeds. This arises out of the fact that, aside from the delay in the flow of data until the result of the comparison by the comparator is obtained, a further delay is necessary, because during an operating cycle the comparator can only operate upon the unit of information of a single pair of parallel system units.
This difficulty could be avoided by allocating comparators permanently to all groups of identical system units which are to be paralleled during the operation. In this case, special twin or multiple terminals would be needed in each system unit communicating with other parallel operating system unit. This will be explained in greater detail with reference to a twin terminal.
In this case, two inlets are assigned to a particular signal, e.g. the "cycle request" signal, which is transmitted by two processing units to a storage unit. These inlets are connected with the storage unit and with the comparator. These inlets must be coupled within the storage unit by means of gate circuits. Thus, such a twin terminal requires not only additional technical effort, which is proportional to the number of parallel terminals to be provided, but it also causes a loss of speed as a result of the comparison and the coupling of the inlets. Moreover, special twin terminals cannot be separated without changing the hardware. Hence, twin terminals also reduce the adaptability of the system to various applications.
An important object of the invention is, therefore, the provision of a program-controlled data processor of the type discussed hereinabove which avoids the difficulties of the prior art methods for paralleling system units.